问：ARM Cortex-M0 I2C SERIAL INTERFACE CONTROLLER (MASTER/SLAVE)
答：Q1: Is one byte for I2C address? Why the I2C timing address of 24C06 EEPROM is one byte?
A1: User confuses the I2C slave address and EEPROM address.
Q2: How to handle the I2C bus hung up in slave mode?
A2: Please reset the I2C peripheral by software.
Q3: What is the value for the pull-high resistor on the I2C bus?
A3: Please add 4.7 kohm pull-high resistor on the I2C bus.
问：ARM CORTEX-M0 GENERAL PURPOSE I/O
答：
Q1: How many external interrupt sources does the NuMicro™ family chip can support?
A1: All of the GPIO can generate the external interrupt.
Q2: What is the machine cycle number for the GPIO toggling?
A2: There are about 11 machine cycles for medium density of NUC100 series, but about 7 machine cycles for low density of NUC100 series and M051 series.
Q3: What is the default state of GPIO after reset?
A3: It is in Quasi-bidirectional mode with weakly pull high (>100K).
Q4: Are all of GPIO the multifunction pins?
A4: No, but most part of GPIO are the multifunction pins. Please refer the Pin Description in the datasheet or TRM of the chip.
Q5: Do all of GPIO pins can be set as the sources to wake up chip?
A5: Yes, all of GPIO pins can be set as the sources to wake up the chip.
问：ARM CORTEX-M0 USB DEVICE CONTROLLER(3)
答：
Q7: What kinds of USB that NUC100 series provide?
A7: It just provides the USB Device (USB2.0 full speed), but Nuvoton will create the new chips that include the USB Host and USB Device (USB2.0 high speed) in future.
Q8: Does NuMicro ™ family chip pass the USB certification?
A8: Yes, please visit the Nuvoton NuMicro™ family website www.nuvoton.com/NuMicro
Q9: Does Nuvoton can provide the VID and PID for customers?
A9: No, the customers need to apply for the VID and PID for your USB applications by yourself.
问：ARM CORTEX-M0 USB DEVICE CONTROLLER(2)
答：
Q4: What sample codes of USB can be provided by Nuvoton?
A4: HID, HID Transfer, UAC (USB Audio Class), UVC, Virtual COM Port, UDC (USB Device Control), HID IO. Q5: What are the transfer types of USB?
A5: Control, Interrupt, Bulk, Isochronous. Q6: How much endpoints can be provided for the USB device in NUC100 series?
A6: It provides 6 endpoints for the USB device.
问：ARM CORTEX-M0 USB DEVICE CONTROLLER(1)
答：
Q1: Does all NuMicro™ family chips provide the USB functions?
A1: No, only NUC100 series provide the USB functions, but M051 series doesn't provide the USB functions.
Q2: Does it always use the interrupt for USB HID?
A2: Yes.
Q3: How to disable the USB 1.5 Kohm pull high resistor?
A3: Disable the control bit in USB register.
问：新唐CORTEX-M0 CLOCK CONTROLLER(2)
答：Q4: How to set USB = 48 MHz, HCLK = 32 MHz for CPU and SPICLK = 16 MHz for SPI Master?
A4:
Enable PLL and set PLL output = 96 MHz
USB = PLL output / 2 = 48 MHz
HCLK = PLL output / 3 = 32 MHz
SPICLK = HCLK / 2 = 16 MHz Q5: Which peripherals have the independent clock sources can be selected?
A5: Watchdog Timer, ADC converter, Timer, UART, CAN, PWM and I2S.
Q6: Which clocks can still work in deep sleep mode (power down mode)?
A6: The external 32 KHz crystal and the internal 10 KHz RC.
问：ARM CORTEX™-M0 CORE(1)
答：Q1: Interrupt cycle from interrupt happens to the first instruction of ISR?
A1: Total 24 cycles.
Q2: What is the HCLK?
A2: It is the clock of AHB bus.
Q3: What is the APB arbiter?
A3: To judge the priority of APB peripherals.
Q4: What are the AHB , APB and AHB-Lite?
A4: AHB means the Advanced High-Performance Bus, APB means the Advanced Peripheral Bus, and AHB-Lite is a subset of the full AHB specification. For further details, please visit the ARM® website http://infocenter.arm.com/help/index.jsp.
问：ARM CORTEX™-M0 CORE(2)
答：Q5: How to clarify the hard fault exception?
A5: Please add the code as below and set the breakpoint at __NOP. User can step run to clarify the hardfault issue after exiting HardFault_Handler.
Q6: What is instruction cycle of Cortex™-M0 ?
A6: Please refer the Cortex™ -M0 Technical Reference Manual from the ARM® website http://infocenter.arm.com/help/index.jsp.
Q7: Does the chip have a unique CPUID? How to do if the user wants to use an unique ID to encrypt his chip?
A7: No, user can write a number in chip's given address of APROM.
Q8: What is NVIC? How many levels of priority it supports
A8: NVIC is the Nested Vectored Interrupt Controller, and it supports 4 levels of priority.
问：NUVOTON CORTEX-M0 SYSTEM MANAGER
答：Q1: Does NuMicro™ family series support the external SRAM through the I/O pins?
A1: Partially supported. Please check the selection guide of NuMicro™ family to check which devices can support the external bus interface (EBI).
Q2: How to enter the sleep (idle mode) and deep sleep mode (power down mode)?
A2: Please follow the commands as below to enter the sleep and deep sleep mode.
Sleep mode Deep Sleep mode
UNLOCKREG(); UNLOCKREG();
SCB->SCR = 4; SCB->SCR = 4;
SYSCLK->PWRCON.WINT_EN = 0; SYSCLK->PWRCON.WINT_EN = 0;
SYSCLK->PWRCON.PD_WAIT_CPU = 1; SYSCLK->PWRCON.PD_WAIT_CPU = 1;
SYSCLK->PWRCON.PWR_DOWN = 0; SYSCLK->PWRCON.PWR_DOWN = 1;
LOCKREG(); LOCKREG();
__WFI(); __WFI();
问：新唐CORTEX-M0 CLOCK CONTROLLER(1)
答：Q1: Does NuMicro™ family provide the clock output pin to monitor the internal clock?
A1: Yes, it does. But it depends on the part number.
Q2: Does NuMicro™ family provide the flag to monitor the internal clock is stable or not?
A2: Yes, but only for the new chip, please refer the related Technical Reference Manual for further details.
Q3: Does the internal 22 MHz RC can be set as the clock source of PLL to generate the 48 MHz for the USB controller?
A3: Not recommended, because the internal 22 MHz RC precision will generate the difference for the 48 MHz output of PLL.
